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titleScan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems
DOIinfo:doi/10.1109/TNS.2008.2000772
Reference URLhttp://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4636968
Author(jpn)柳川, 善光; 小林, 大輔; 池田, 博一; 齋藤, 宏文; 廣瀬, 和之
Author(eng)Yanagawa, Y.; Kobayashi, Daisuke; Ikeda, Hirokazu; Saito, Hirobumi; Hirose, Kazuyuki
Author Affiliation(jpn)宇宙航空研究開発機構宇宙科学研究本部 (JAXA)(ISAS); 宇宙航空研究開発機構宇宙科学研究本部 (JAXA)(ISAS); 宇宙航空研究開発機構宇宙科学研究本部 (JAXA)(ISAS); 宇宙航空研究開発機構宇宙科学研究本部 (JAXA)(ISAS)
Author Affiliation(eng)Department of Electronic Engineering, School of Engineering, The University of Tokyo; Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency (JAXA)(ISAS); Graduate University for Advanced Studies; Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency (JAXA)(ISAS); Graduate University for Advanced Studies; Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency (JAXA)(ISAS); Department of Electronic Engineering, School of Engineering, The University of Tokyo; Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency (JAXA)(ISAS); Graduate University for Advanced Studies
Issue Date2008
PublisherThe Institute of Electrical and Electronic Engineers (IEEE)
Publication titleIEEE Transactions on Nuclear Science
Volume55
Issue4
Start page1947
End page1952
Publication date2008
Languageeng
Document TypeJournal Article
JAXA Category学術雑誌論文
ISSN0018-9499
SHI-NOPAIS08149000
URIhttps://repository.exst.jaxa.jp/dspace/handle/a-is/14140


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