| タイトル | Description and Simulation of a Fast Packet Switch Architecture for Communication Satellites |
| 本文（外部サイト） | http://hdl.handle.net/2060/19960009102 |
| 著者（英） | Lizanich, Paul J.; Quintana, Jorge A. |
| 著者所属（英） | NASA Lewis Research Center |
| 発行日 | 1995-12-01 |
| 言語 | eng |
| 内容記述 | The NASA Lewis Research Center has been developing the architecture for a multichannel communications signal processing satellite (MCSPS) as part of a flexible, low-cost meshed-VSAT (very small aperture terminal) network. The MCSPS architecture is based on a multifrequency, time-division-multiple-access (MF-TDMA) uplink and a time-division multiplex (TDM) downlink. There are eight uplink MF-TDMA beams, and eight downlink TDM beams, with eight downlink dwells per beam. The information-switching processor, which decodes, stores, and transmits each packet of user data to the appropriate downlink dwell onboard the satellite, has been fully described by using VHSIC (Very High Speed Integrated-Circuit) Hardware Description Language (VHDL). This VHDL code, which was developed in-house to simulate the information switching processor, showed that the architecture is both feasible and viable. This paper describes a shared-memory-per-beam architecture, its VHDL implementation, and the simulation efforts. |
| NASA分類 | COMMUNICATIONS AND RADAR |
| レポートNO | 96N16268
NASA-TM-107104
NAS 1.15:107104
E-9994
AIAA PAPER 96-1127
NIPS-95-06836 |
| 権利 | No Copyright |
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