| タイトル | An improved distributed arithmetic architecture |
| 本文（外部サイト） | http://hdl.handle.net/2060/19940013876 |
| 著者（英） | Lynn, D. W.; Guo, X. |
| 著者所属（英） | Idaho Univ. |
| 発行日 | 1991-01-01 |
| 言語 | eng |
| 内容記述 | Speed requirements have been, and will continue to be, a major consideration in the design of hardware to implement digital signal processing functions like digital filters and transforms like the DFT and DCT. The conventional approach is to increase speed by adding hardware and increasing chip area. The real challenge is to save chip area while still maintaining high speed performance. The approach we propose is based on the distributed arithmetic implementation (DA) of digital filters. The improvement is based on two observations. Firstly, a single memory element can replace several identical memory elements in a fully parallel DA implementation. Secondly, truncation or rounding may be introduced into the computation at strategic points without increasing error unduly. Both of these approaches can be used to attain area savings without impairing speed of operation. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 94N18349 |
| 権利 | No Copyright |
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