| タイトル | Design and qualification of the SEU/TD Radiation Monitor chip |
| 本文（外部サイト） | http://hdl.handle.net/2060/19930013852 |
| 著者（英） | Hicks, Kenneth A.; Buehler, Martin G.; Soli, George A.; Zamani, Nasser; Blaes, Brent R. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1992-10-01 |
| 言語 | eng |
| 内容記述 | This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 93N23041
NASA-CR-192797
NAS 1.26:192797
JPL-PUBL-92-18 |
| 権利 | No Copyright |
