| タイトル | BETA: Behavioral testability analyzer and its application to high-level test generation and synthesis for testability |
| 本文（外部サイト） | http://hdl.handle.net/2060/19930004381 |
| 著者（英） | Chen, Chung-Hsing |
| 著者所属（英） | Illinois Univ. |
| 発行日 | 1992-11-19 |
| 言語 | eng |
| 内容記述 | In this thesis, a behavioral-level testability analysis approach is presented. This approach is based on analyzing the circuit behavioral description (similar to a C program) to estimate its testability by identifying controllable and observable circuit nodes. This information can be used by a test generator to gain better access to internal circuit nodes and to reduce its search space. The results of the testability analyzer can also be used to select test points or partial scan flip-flops in the early design phase. Based on selection criteria, a novel Synthesis for Testability approach call Test Statement Insertion (TSI) is proposed, which modifies the circuit behavioral description directly. Test Statement Insertion can also be used to modify circuit structural description to improve its testability. As a result, Synthesis for Testability methodology can be combined with an existing behavioral synthesis tool to produce more testable circuits. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 93N13569
NASA-CR-191282
NAS 1.26:191282
UILU-ENG-92-2243
CRHC-92-25 |
| 権利 | Copyright, Distribution under U.S. Government purpose rights |
