| タイトル | Integrated Vertical Bloch Line (VBL) memory |
| 本文（外部サイト） | http://hdl.handle.net/2060/19910014738 |
| 著者（英） | Wu, J. C.; Katti, R. R.; Stadler, H. L. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1991-01-01 |
| 言語 | eng |
| 内容記述 | Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid state, block access, VLSI memory which offers the potential of 1 Gbit/sq cm areal storage density, data rates of hundreds of megabits/sec, and submillisecond average access time simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBLs are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of BVL pairs are used to store binary information. At present, efforts are being directed at developing a single chip memory using 25 Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. The current design architecture, functional elements, and supercomputer simulation results are described which are used to assist the design process. |
| NASA分類 | COMPUTER OPERATIONS AND HARDWARE |
| レポートNO | 91N24051 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/132539 |
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