| タイトル | Phase-lock-loop application for fiber optic receiver |
| 本文（外部サイト） | http://hdl.handle.net/2060/19910012122 |
| 著者（英） | Ruggles, Stephen L.; Wills, Robert W. |
| 著者所属（英） | NASA Langley Research Center |
| 発行日 | 1991-02-01 |
| 言語 | eng |
| 内容記述 | Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 91N21435
NASA-TM-102776
NAS 1.15:102776 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/133155 |
