| タイトル | On testing VLSI chips for the big Viterbi decoder |
| 本文（外部サイト） | http://hdl.handle.net/2060/19890010087 |
| 著者（英） | Hsu, I. S. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1989-02-15 |
| 言語 | eng |
| 内容記述 | A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 89N19458 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/143044 |
|
