| タイトル | A new VLSI architecture for a single-chip-type Reed-Solomon decoder |
| 本文（外部サイト） | http://hdl.handle.net/2060/19890010084 |
| 著者（英） | Hsu, I. S.; Truong, T. K. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1989-02-15 |
| 言語 | eng |
| 内容記述 | A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain. |
| NASA分類 | COMMUNICATIONS AND RADAR |
| レポートNO | 89N19455 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/143047 |
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