| タイトル | The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder |
| 本文（外部サイト） | http://hdl.handle.net/2060/19880003315 |
| 著者（英） | Shao, H. M.; Deutsch, L. J.; Hsu, I. S. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1987-11-15 |
| 言語 | eng |
| 内容記述 | The very large-scale integration (VLSI) architecture of a single chip (255, 223) Reed-Solomon decoder for decoding both errors and erasures is described. A decoding failure detection capability is also included in this system so that the decoder will recognize a failure to decode instead of introducing additional errors. This could happen whenever the received word contains too many errors and erasures for the code to correct. The number of transistors needed to implement this decoder is estimated at about 75,000 if the delay for received message is not included. This is in contrast to the older transform decoding algorithm which needs about 100,000 transistors. However, the transform decoder is simpler in architecture than the time decoder. It is therefore possible to implement a single chip (255, 223) Reed-Solomon decoder with today's VLSI technology. An implementation strategy for the decoder system is presented. This represents the first step in a plan to take advantage of advanced coding techniques to realize a 2.0 dB coding gain for future space missions. |
| NASA分類 | COMMUNICATIONS AND RADAR |
| レポートNO | 88N12697 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/148174 |
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