| タイトル | Error propagation in a digital avionic processor: A simulation-based study |
| 本文（外部サイト） | http://hdl.handle.net/2060/19860007881 |
| 著者（英） | Lomelino, D.; Iyer, R. K. |
| 著者所属（英） | Illinois Univ. |
| 発行日 | 1986-01-01 |
| 言語 | eng |
| 内容記述 | An experimental analysis to study error propagation from the gate to the chip level is described. The target system is the CPU in the Bendix BDX-930, an avionic miniprocessor. Error activity data for the study was collected via a gate-level simulation. A family of distributions to characterize the error propagation, both within the chip and at the pins, was then generated. Based on these distributions, measures of error propagation and severity were defined. The analysis quantifies the dependency of the measured error propagation on the location of the fault and the type of instruction/microinstruction executed. |
| NASA分類 | AIRCRAFT INSTRUMENTATION |
| レポートNO | 86N17351
NAS 1.26:176501
NASA-CR-176501 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/154868 |
