| タイトル | Virtex-II Pro SEE Test Methods and Results |
| 本文（外部サイト） | http://hdl.handle.net/2060/20040170470 |
| 著者（英） | Howard, James; Powell, Wesley; Petrick, David |
| 著者所属（英） | NASA Goddard Space Flight Center |
| 発行日 | 2004-09-02 |
| 言語 | eng |
| 内容記述 | The Xilinx Virtex-II Pro is a platform FPGA that embeds multiple microprocessors within the fabric of an SRAM-based reprogrammable FPGA. The variety and quantity of resources provided by this family of devices make them very attractive for spaceflight applications. However, these devices will be susceptible to single event effects (SEE), which must be mitigated. To use the Virtex-II Pro reliably in space applications, these devices must first be tested to determine if they are susceptible to single event latchup (SEL), the degree to which they are susceptible to single event upsets (SEU) and single event transients (SET), and how these effects are manifested in the device. With this information, mitigations schemes can be developed and tested that address the specific susceptiblities of these devices. This initial SEE test uses a commercial off the shelf Virtex-II Pro evaluation board, with a single processor XC2VP7 FPGA. The FPGA on this board is an acid etched device, which can be partially covered with a shield. The shield covers a portion of the logic, routing, and memory resources along with some of the RocketIO transceivers. The processor, along with a large portion of logic, routing, memory, and transceivers are left exposed. This test will be performed at the Cyclotron Laboratories at Texas A&M University and Michigan State University using ions of varying energy levels and fluencies. |
| NASA分類 | Electronics and Electrical Engineering |
| 権利 | No Copyright |
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