| タイトル | Integrating Cache Performance Modeling and Tuning Support in Parallelization Tools |
| 本文（外部サイト） | http://hdl.handle.net/2060/20020073380 |
| 著者（英） | Saini, Subhash; Yan, Jerry; Waheed, Abdul |
| 著者所属（英） | MRJ Technology Solutions, Inc. |
| 発行日 | 1998-01-01 |
| 言語 | eng |
| 内容記述 | With the resurgence of distributed shared memory (DSM) systems based on cache-coherent Non Uniform Memory Access (ccNUMA) architectures and increasing disparity between memory and processors speeds, data locality overheads are becoming the greatest bottlenecks in the way of realizing potential high performance of these systems. While parallelization tools and compilers facilitate the users in porting their sequential applications to a DSM system, a lot of time and effort is needed to tune the memory performance of these applications to achieve reasonable speedup. In this paper, we show that integrating cache performance modeling and tuning support within a parallelization environment can alleviate this problem. The Cache Performance Modeling and Prediction Tool (CPMP), employs trace-driven simulation techniques without the overhead of generating and managing detailed address traces. CPMP predicts the cache performance impact of source code level "what-if" modifications in a program to assist a user in the tuning process. CPMP is built on top of a customized version of the Computer Aided Parallelization Tools (CAPTools) environment. Finally, we demonstrate how CPMP can be applied to tune a real Computational Fluid Dynamics (CFD) application. |
| NASA分類 | Computer Operations and Hardware |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/224427 |
