| タイトル | Automated synthesis and verification of configurable DRAM blocks for ASIC's |
| 著者（英） | Kwatra, S. C.; Eldin, A. G.; Pakkurti, M.; Jamali, M. |
| 著者所属（英） | Toledo Univ. |
| 発行日 | 1993-01-01 |
| 言語 | eng |
| 内容記述 | A highly flexible embedded DRAM compiler is developed which can generate DRAM blocks in the range of 256 bits to 256 Kbits. The compiler is capable of automatically verifying the functionality of the generated DRAM modules. The fully automated verification capability is a key feature that ensures the reliability of the generated blocks. The compiler's architecture, algorithms, verification techniques and the implementation methodology are presented. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 94N21123 |
| 権利 | No Copyright |
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