| タイトル | Reliable interface design for combining asynchronous and synchronous circuits |
| 著者（英） | Josephson, Lueli; Gopalakrishan, Ganesh; Hurdle, John F.; Brunvand, Erik L. |
| 著者所属（英） | Utah Univ. |
| 発行日 | 1993-01-01 |
| 言語 | eng |
| 内容記述 | In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 94N21119 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/229261 |
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