| タイトル | Multiple Embedded Processors for Fault-Tolerant Computing |
| 本文（外部サイト） | http://hdl.handle.net/2060/20110016476 |
| 著者（英） | Watson, Robert; Wang, Mandy; Katanyoutanant, Sunant; Burke, Gary; Bolotin, Gary |
| 著者所属（英） | California Inst. of Tech. |
| 発行日 | 2005-12-01 |
| 言語 | eng |
| 内容記述 | A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them. |
| NASA分類 | Man/System Technology and Life Support |
| レポートNO | NPO-40575 |
| 権利 | Copyright, Distribution as joint owner in the copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/269238 |
