| タイトル | Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM |
| 著者（英） | Bernstein, Joseph; White, Mark; Huang, Bing; Nguyen, Duc; Talmor, Michael; Chen, Yuan; Heidecker, Jason; Gur, Zvi; Qin, Jin |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 2005-10-17 |
| 言語 | eng |
| 内容記述 | As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data. |
| NASA分類 | Electronics and Electrical Engineering |
| 権利 | Copyright |
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