| タイトル | Fault-Tolerant Flight Computer |
| 著者（英） | Chau, Savio |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1996-04-01 |
| 言語 | eng |
| 内容記述 | In design concept for adaptive, fault-tolerant flight computer, upon detection of fault in either processor, surviving processor assumes responsibility for both equipment systems. Possible because of cross-strapping between processors, memories, and input/output units. Concept also applicable to other computing systems required to tolerate faults and in which partial loss of processing speed or functionality acceptable price to pay for continued operation in event of faults. |
| NASA分類 | ELECTRONIC SYSTEMS |
| レポートNO | 96B10160
NPO-19675 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/304830 |
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