| タイトル | Mapping Pixel Windows To Vectors For Parallel Processing |
| 著者（英） | Duong, Tuan A. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1996-03-01 |
| 言語 | eng |
| 内容記述 | Mapping performed by matrices of transistor switches. Arrays of transistor switches devised for use in forming simultaneous connections from square subarray (window) of n x n pixels within electronic imaging device containing np x np array of pixels to linear array of n(sup2) input terminals of electronic neural network or other parallel-processing circuit. Method helps to realize potential for rapidity in parallel processing for such applications as enhancement of images and recognition of patterns. In providing simultaneous connections, overcomes timing bottleneck or older multiplexing, serial-switching, and sample-and-hold methods. |
| NASA分類 | ELECTRONIC SYSTEMS |
| レポートNO | 96B10114
NPO-19431 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/305175 |
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