| タイトル | A VLSI decomposition of the deBruijn graph |
| 著者（英） | Pollara, Fabrizio; Dolinar, Sam; Mceliece, Robert; Collins, Oliver |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1992-10-01 |
| 言語 | eng |
| 内容記述 | The nth order deBruijn graph Bn is the state diagram for an n-stage binary shift register. It is a directed graph with 2 to the n vertices, each labeled with an n-bit binary string, and 2 to the n+1 edges, each labeled with an (n+1)-bit binary string. It is shown that Bn can be built by appropriately connecting together with extra edges many isomorphic copies of a fixed graph, which is called a building block for Bn. The efficiency of such a building block is refined as the fraction of the edges of Bn which are present in the copies of the building block. It is then shown that for any alpha less than 1, there exists a graph which is a building block for Bn of efficiency greater than alpha for all sufficiently large n. The results are illustrated by showing how a special hierarchical family of building blocks has been used to construct a very large Viterbi decoder which will be used on the Galileo mission. |
| NASA分類 | COMPUTER PROGRAMMING AND SOFTWARE |
| レポートNO | 93A44966 |
| 権利 | Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/316329 |
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