| タイトル | Cascaded VLSI Chips Help Neural Network To Learn |
| 著者（英） | Duong, Tuan A.; Thakoor, Anilkumar P.; Daud, Taher |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1993-12-01 |
| 言語 | eng |
| 内容記述 | Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network. |
| NASA分類 | ELECTRONIC SYSTEMS |
| レポートNO | 93B10760
NPO-18645 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/323042 |
|
