| タイトル | Stacked-Gate FET's For Analog Memory Elements |
| 著者（英） | Moopenn, Alexander W.; Thakoor, Anilkumar P. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1991-07-01 |
| 言語 | eng |
| 内容記述 | Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device. |
| NASA分類 | ELECTRONIC COMPONENTS AND CIRCUITS |
| レポートNO | 91B10294
NPO-17627 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/353041 |
|
