| タイトル | Compiler-directed cache management in multiprocessors |
| 著者（英） | Cheong, Hoichi; Veidenbaum, Alexander V. |
| 著者所属（英） | Illinois Univ. |
| 発行日 | 1990-06-01 |
| 言語 | eng |
| 内容記述 | The necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory multiprocessor systems with interconnection networks and a large number of processors. Results of trace-driven simulations conducted on numerical benchmark routines to compare the performance of the three schemes are presented. |
| NASA分類 | COMPUTER SYSTEMS |
| レポートNO | 90A47430 |
| 権利 | Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/354198 |
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