| タイトル | Radiation Hardening of Computers |
| 著者（英） | Treece, R. K.; Hewlett, F. W.; Nichols, D. K.; Zoutendyk, J. A.; Smith, L. S.; Giddings, A. E. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1986-05-01 |
| 言語 | eng |
| 内容記述 | Single-event upsets reduced by use of oversize transistors. Computers made less susceptible to ionizing radiation by replacing bipolar integrated circuits with properly designed, complementary metaloxide-semiconductor (CMOS) circuits. CMOS circuit chips made highly resistant to single-event upset (SEU), especially when certain feedback resistors are incorporated. Redesigned chips also consume less power than original chips. |
| NASA分類 | ELECTRONIC SYSTEMS |
| レポートNO | 86B10214
NPO-16767 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/388961 |
|
