| タイトル | Latchup in CMOS Integrated Circuits |
| 著者（英） | Nichols, D. K.; Soliman, K. A. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech. |
| 発行日 | 1985-10-01 |
| 言語 | eng |
| 内容記述 | Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type. |
| NASA分類 | ELECTRONIC SYSTEMS |
| レポートNO | 85B10170
NPO-16304 |
| 権利 | No Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/395882 |
