| タイトル | Flip-flop resolving time test circuit |
| 著者（英） | Rosenberger, F.; Chaney, T. J. |
| 著者所属（英） | Washington Univ. |
| 発行日 | 1982-08-01 |
| 言語 | eng |
| 内容記述 | Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 82A41533 |
| 権利 | Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/409359 |
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