| タイトル | Integrated circuit process and design rule evaluation techniques |
| 著者（英） | Sarace, J. C.; Ipri, A. C. |
| 著者所属（英） | RCA Labs. |
| 発行日 | 1977-09-01 |
| 言語 | eng |
| 内容記述 | A technique is described for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits. Test arrays were developed to isolate various critical processing steps in a fabrication sequence and a statistical evaluation of these steps was carried out that related yield or success in achieving a desired result to the number of times the results were attempted. It was found that, in general, yield is a sensitive function of physical dimensions as is the packing density of a particular array. It is, therefore, possible to generate an optimum set of physical dimensions or design rules that maximize the expected number of working circuits on a wafer. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 78A13119 |
| 権利 | Copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/434824 |
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