0.25μmLSI多層配線技術

Abstract

This paper describes multilevel interconnection technology for 0.25 micrometer CMOS LSIs (Complementary Metal-Oxide-Semiconductor Large Scale Integrations). A new selective CVD (Chemical Vapor Deposition) process was developed to form W cladding with low sheet resistance and low silicon consumption. P-CVD (Plasma-CVD) SiO2/O3-TEOS (Tetraethoxysilane)-BPSG (Borophosphosilicate Glass)/P-CVD SiO2 was proposed as an interlayer insulator material with high cracking resistance, high gap-filling ability, and high resistance to hot carrier degradation. Its high reliability was also confirmed. The CMP (Chemical and Mechanical Polishing) loading effect was studied. It was demonstrated that the loading effect can be suppressed by increasing the wafer speed during CMP. Integration of a laminated AlCu structure, interlayer insulator planarization, laminated interlayer structure, and fine line fabrication by reactive ion etching results in electromigration resistance higher than that of conventional laminated interconnections. A gate array LSI with 300 K having the same pitch was successfully fabricated using process integration of element technologies for fully planarized multi-level interconnection.

微細化が進むCMOSLSI(相補型金属-酸化物-半導体大規模集積回路)の多層配線は、高性能化、高信頼化、高歩溜まり化、低コスト化、短TAT(ターンアラウンドタイム)化などの要求がますます高まっている。本論文では0.25マイクロメートルCMOSLSI用多層配線技術の実用化のために研究開発を進めた要素技術と総合化技術、さらにLSIへの導入結果について述べる。高ホットキャリア耐性および高クラック耐性の層間絶縁膜構成の検討および評価結果を述べ、さらにローディング効果を低減したグローバル平坦化CMP(化学機械研磨)技術、スタックドビアを含むグローバル平坦化多層配線の高信頼化、低層抵抗および低Si消費量のWの自己整合コンタクト張付け技術などについての検討結果を述べる。要素技術の総合化により、等ピッチ、4層配線の300KのCMOSゲートアレイLSIに適用し、高性能および高信頼性を確認した。