| タイトル | N channel JFET based digital logic gate structure |
| 本文（外部サイト） | http://hdl.handle.net/2060/20100015620 |
| 著者（英） | Krasowski, Michael J. |
| 著者所属（英） | NASA Headquarters |
| 発行日 | 2010-03-30 |
| 言語 | eng |
| 内容記述 | A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures. |
| NASA分類 | Electronics and Electrical Engineering |
| 権利 | No Copyright |
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