| タイトル | Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays |
| 本文（外部サイト） | http://hdl.handle.net/2060/20090032149 |
| 著者（英） | Ewin, Audrey J.; Jhabvala, Christine; Costen, Nicholas; Babu, Sachi; Franz, David E.; Jhabvala, Murzy; Zincke, Christian; Snodgrass, Stephen |
| 著者所属（英） | NASA Goddard Space Flight Center |
| 発行日 | 2009-09-01 |
| 言語 | eng |
| 内容記述 | The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices. |
| NASA分類 | Technology Utilization and Surface Transportation |
| レポートNO | GSC- 15665-1 |
| 権利 | Copyright, Distribution as joint owner in the copyright |
| URI | https://repository.exst.jaxa.jp/dspace/handle/a-is/509210 |
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