| タイトル | Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits |
| 本文（外部サイト） | http://hdl.handle.net/2060/20080007429 |
| 著者（英） | Nixon, Robert H.; Buehler, Martin G.; Blaes, Brent R.; Soli, George A. |
| 著者所属（英） | Lynx Golf, Inc. |
| 発行日 | 1995-03-07 |
| 言語 | eng |
| 内容記述 | A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate. |
| NASA分類 | Electronics and Electrical Engineering |
| 権利 | No Copyright |
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