| タイトル | Digital logic optimization using selection operators |
| 本文（外部サイト） | http://hdl.handle.net/2060/20080005172 |
| 著者（英） | Cameron, Eric G.; Gambles, Jody W.; Whitaker, Sterling R.; Miles, Lowell H. |
| 著者所属（英） | Science and Technology Corp. |
| 発行日 | 2004-08-17 |
| 言語 | eng |
| 内容記述 | According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more. |
| NASA分類 | Electronics and Electrical Engineering |
| 権利 | No Copyright |
|
