| タイトル | Chip connectivity verification program |
| 本文（外部サイト） | http://hdl.handle.net/2060/20080004490 |
| 著者（英） | Riley, Josh; Patterson, George |
| 著者所属（英） | California Inst. of Tech. |
| 発行日 | 1999-09-07 |
| 言語 | eng |
| 内容記述 | A method for testing electrical connectivity between conductive structures on a chip that is preferably layered with conductive and nonconductive layers. The method includes determining the layer on which each structure is located and defining the perimeter of each structure. Conductive layer connections between each of the layers are determined, and, for each structure, the points of intersection between the perimeter of that structure and the perimeter of each other structure on the chip are also determined. Finally, electrical connections between the structures are determined using the points of intersection and the conductive layer connections. |
| NASA分類 | Computer Operations and Hardware |
| 権利 | No Copyright |
