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タイトルIntelligent subsystem interface for modular hardware system
本文(外部サイト)http://hdl.handle.net/2060/20080004044
著者(英)Schneiderwind, Michael J.; Krening, Douglas N.; Lannan, Gregory B.; Schneiderwind, Robert A.; Caffrey, Robert T.
著者所属(英)First Pass, Inc.
発行日2000-09-19
言語eng
内容記述A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.
NASA分類Electronics and Electrical Engineering
権利No Copyright


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