| タイトル | Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets |
| 本文（外部サイト） | http://hdl.handle.net/2060/19920006978 |
| 著者（英） | Zoutendyk, John A. |
| 著者所属（英） | Jet Propulsion Lab., California Inst. of Tech.|NASA Pasadena Office |
| 発行日 | 1991-12-10 |
| 言語 | eng |
| 内容記述 | Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction. |
| NASA分類 | ELECTRONICS AND ELECTRICAL ENGINEERING |
| レポートNO | 92N16196 |
| 権利 | No Copyright |
