| タイトル | VLSI binary updown counter |
| 本文（外部サイト） | http://hdl.handle.net/2060/19900012209 |
| 著者（英） | Hsu, In-Shek; Truong, Trieu-Kie; Reed, Irving S. |
| 著者所属（英） | NASA Pasadena Office |
| 発行日 | 1989-07-04 |
| 言語 | eng |
| 内容記述 | A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equation: A(sub n)(t) = A(sub n)(t - 1) exclusive OR (U AND P(sub n)) inclusive OR (D AND Q(sub n)), where A(sub n)(t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U = 0 and D = 1, the input is -1 and if U = 1 and D = 0, the input is +1. P(sub n) represents a product of A(sub k)'s for 1 is less than or equal to k is less than or equal to -1, while Q(sub n) represents the product of bar A's for 1 is less than or equal to K is less than or equal to n - 1, where bar A(sub k) is the complement of A(sub k) and P(sub n) and Q(sub n) are expressed as the following two equations: P(sub n) = A(sub n - 1) A(sub n - 2)...A(sub 1) and Q(sub n) = bar A(sub n - 1) bar A(sub n - 2)...bar A(sub 1), which can be written in recursive form as P(sub n) = P(sub n - 1) AND bar A(sub n - 1) and Q(sub n) = Q(sub n - 1) AND bar A(sub n - 1) with the initial values P(sub 1) = 1 and Q(sub 1) = 1. |
| NASA分類 | COMPUTER OPERATIONS AND HARDWARE |
| レポートNO | 90N21525 |
| 権利 | No Copyright |
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