| タイトル | Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices |
| 本文（外部サイト） | http://hdl.handle.net/2060/20150018112 |
| 著者（英） | Phan, A.; Pellish, J.; Campola, M.; Berg, M.; LaBel, K.; Seidleck, C.; Kim, H. |
| 著者所属（英） | NASA Goddard Space Flight Center |
| 発行日 | 2015-07-13 |
| 言語 | eng |
| 内容記述 | Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection. |
| NASA分類 | Electronics and Electrical Engineering |
| レポートNO | GSFC-E-DAA-TN24990 |
| 権利 | Copyright, Distribution as joint owner in the copyright |
