| タイトル | Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect |
| 本文（外部サイト） | http://hdl.handle.net/2060/20160005308 |
| 著者（英） | Chang, Carl W.; Chen, Liangyu; Beheim, Glenn M.; Lukco, Dorothy; Prokop, Norman F.; Neudeck, Philip G.; Spry, David J.; Krasowski, Michael J. |
| 著者所属（英） | NASA Glenn Research Center |
| 発行日 | 2015-10-04 |
| 言語 | eng |
| 内容記述 | Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished. |
| NASA分類 | Electronics and Electrical Engineering |
| レポートNO | GRC-E-DAA-TN26971 |
| 権利 | Copyright, Distribution as joint owner in the copyright |
