| タイトル | Unification of Multiple Gated Flip-Flops for Saving the Power Consumption of Register Circuits |
| 本文（外部サイト） | https://catalog.lib.kyushu-u.ac.jp/opac_download_md/16766/okuhira09_2.pdf |
| 参考URL | http://hdl.handle.net/2324/16766 |
| 著者（英） | Okuhira, Takumi; Ishihara, Tohru |
| 発行日 | 2010-03-10 |
| 刊行物名 | SLRC 論文データベース |
| 刊行年月日 | 2010-02 |
| 言語 | eng |
| 内容記述 | Since the clock power consumption in today’s processors is considerably large, reducing the clock power consumption contributes to the reduction of the total power consumption in the processors. Recently, a gated flip-flop is proposed for reducing the clock power consumption of flip-flop circuits. The gated flip-flop employs a clock-gating circuit which cuts off an internal clock signal if the data stored in the flip-flop does not need to be updated. This reduces the clocking power consumption. However, the power dissipated in the clock-gating circuit is still large. For reducing the power dissipated in the clock-gating circuit, this paper proposes a technique for unifying the multiple clock-gating circuits, which reduces the overhead of the clock-gating circuit. Experimental results obtained using an RTL model of a commercial embedded processor demonstrate that our technique reduces the power consumption of register circuits in the processor by 44% on an average and 53% at the best case compared to the register circuits composed of the conventional gated flip-flops. |
| 資料種別 | Conference Paper |
| 著者版フラグ | author |
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