| タイトル | Thermal-aware partitioning for 3D FPGAs |
| DOI | info:doi/10.1109/FPL.2012.6339198 |
| 本文（外部サイト） | https://catalog.lib.kyushu-u.ac.jp/opac_download_md/26567/krishna12_1.pdf |
| 参考URL | http://hdl.handle.net/2324/26567 |
| 著者（英） | Chaitanya Nunna, Krishna; Mehdipour, Farhad; Murakami, Kazuaki |
| 発行日 | 2013-06-13 |
| 発行機関など | Institute of Electrical and Electronics Engineers |
| 刊行物名 | Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on |
| 開始ページ | 475 |
| 終了ページ | 476 |
| 刊行年月日 | 2012-08 |
| 言語 | eng |
| 内容記述 | Three-dimensional FPGA is one of the promising innovations which can lead to the reduction in delay, area and power. There is an absolute necessity to develop algorithms and software tools to exploit the advantages of the third dimension, and to solve complex tasks associated with them. Also, thermal issues are cited as critical concern in 3D integration which results in degradation of device performance. In this paper we are proposing an idea for thermal-aware partitioning targeting the power/thermal-aware EDA flow for 3D FPGAs. |
| 資料種別 | Conference Paper |
| 著者版フラグ | author |
| ISBN | 978-1-4673-2255-3
978-1-4673-2257-7 |
| 権利 | (C) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. |
